Verilog
The most recommended of 4 hardware description languages
Widely used to describe digital chips; recommended for parallel modelling and mature tooling. Critics say it is clumsy and was designed for simulation, not synthesis.
Widely used to describe digital chips; recommended for parallel modelling and mature tooling. Critics say it is clumsy and was designed for simulation, not synthesis.
29 people gave an opinion
- recommend it
- 13
- criticize it
- 16
- approval share
- 45%
Recommended in 6 of 13 months
- November 2025: recommended
- December 2025: recommended
- January 2026: recommended
- February 2026: not recommended
- March 2026: recommended
- April 2026: not recommended
- May 2026: not recommended
- June 2026: not recommended
- July 2026: not recommended
- August 2026: not recommended
- September 2026: recommended
- October 2026: not recommended
- November 2026: recommended (month in progress)
Why it doesn’t carry the badge
- 13 people recommend itNeeds 10 or more, met.
- 0.8 recommenders for every criticNeeds 2 to 1 or better, not met.
- Recommended in 6 of 13 monthsNeeds 4 or more, met.
The same three rules apply to every product, and the badge can’t be bought. How the badge works
What people say about it
The reasons people give, with the number of comments that give each one. Open a reason to read what they said.
Why people recommend it
Each mark is one comment
Industry standard for chip design
“Most of industry is still choosing VHDL or Verilog for most greenfield hardware projects.”
Comment from 29 Jan 2026 in “The Sovereign Tech Fund Invests in Scala” “The world's most complex chips are built with it.”
Comment from 30 Mar 2026 in “VHDL's Crown Jewel” Simulation and synthesis match well
“Verilog is about as good at match as you are likely to get, if you stick with the source code approach”
Comment from 23 Dec 2025 in “FPGAs Need a New Future” “yet the Verilog model has given me less issues in practice”
Comment from 30 Mar 2026 in “VHDL's Crown Jewel” “I've never had to chase sim vs synthesis mismatches.”
Comment from 30 Mar 2026 in “VHDL's Crown Jewel” Describes parallel hardware naturally
“in VHDL and Verilog, people have successfully described parallel computations containing billions of concurrent processes”
Comment from 6 Nov 2025 in “I want a good parallel language [video]” “The beauty and the terror of Verilog is the complete, unconstrained parallel nature of it’s default”
Comment from 30 Mar 2026 in “VHDL's Crown Jewel” Efficient for hardware work
“VHDL and Verilog are used because they are excellent languages to describe hardware”
Comment from 23 Dec 2025 in “FPGAs Need a New Future” “Verilog and SystemVerilog allow me to do this efficiently. Warts and all.”
Comment from 30 Mar 2026 in “VHDL's Crown Jewel”
What people warn about
Each mark is one comment
Designed for simulation, not synthesis
“both Verilog and VHDL are languages that were designed for simulation of hardware, and not synthesis of hardware”
Comment from 23 Dec 2025 in “FPGAs Need a New Future” “It's also very lossy (every vendor has reams of coding guides for using it just right with their synthetizer).”
Comment from 7 Sep 2026 in “C Is Not a Low-Level Language (2018)” Clumsy, error-prone, painful to write
“Verilog felt like a joke of a language designed to torment rather than help the user”
Comment from 20 Apr 2026 in “Tim Cook to become Apple Executive Chairman” “writing VHDL or Verilog is universally a fairly miserable experience”
Comment from 25 Oct 2026 in “Making a VGA Driver in SystemVerilog” “All to avoid the painful memories I have of verilog/vhdl.”
Comment from 10 Aug 2026 in “Ask HN: What are you working on? (August 2026)” - Comment from 12 Aug 2026 in “Show HN: Taalas-style on-chip LLM weights on a $250 AMD FPGA (60k tok/s)”
Missing fixed-point and multi-phase clocks
“Verilog's type system is insufficiently expressive to add fixed-point types without changes to the language itself.”
Comment from 30 Mar 2026 in “VHDL's Crown Jewel” “I'm even more amazed that Verilog can't gracefully handle multi-phase clocks”
Comment from 21 Jan 2026 in “Conditions in the Intel 8087 floating-point chip's microcode” Dated tooling and wrong abstraction
“VHDL and Verilog are showing their age with their design as well as ther tooling ecosystem”
Comment from 23 Dec 2025 in “FPGAs Need a New Future” “VHDL and verilog are simply at the wrong abstraction level”
Comment from 30 Mar 2026 in “VHDL's Crown Jewel”
Other hardware description languages people recommend
The three most recommended other hardware description languages, with the same counts for each, so you can compare like for like. The tick on each bar marks the 2 to 1 line the badge needs.
| Product | Recommend | Criticize | Approval | Months | Owned | Badge |
|---|---|---|---|---|---|---|
| VerilogThis page | 13 | 16 | 45% | 6 | — | — |
| Chisel | 7 | 1 | 88% | 4 | — | — |
| SHDL | 6 | 1 | 86% | 1 | — | — |
| Clash (Haskell-to-HDL compiler) | 5 | 0 | 100% | 3 | — | — |
What people said
34 of the 36 comments that mention it, newest first. Each links to the original comment.
“Verilog (or VHDL) along with the wide number of associated tools available for it”
“writing VHDL or Verilog is universally a fairly miserable experience”
“It's also very lossy (every vendor has reams of coding guides for using it just right with their synthetizer).”
“make sure you have documented hours with C/C++, Verilog on Zynq”
“I've only used vhdl and verilog, and liked neither”
“All to avoid the painful memories I have of verilog/vhdl.”
“Verilog is not the best and that's not even the worst part”
“Verilog felt like a joke of a language designed to torment rather than help the user”
“Verilog's type system is insufficiently expressive to add fixed-point types without changes to the language itself.”
“VHDL and verilog are simply at the wrong abstraction level”
“As much as I prefer to write Verilog now”
“I've never had to chase sim vs synthesis mismatches.”
“Verilog gives you enough rope.”
“IMHO Verilog's main problems are that it: a) mixes flops and wires in a confusing way”
“As much as I like Verilog, VHDL is a first class RTL language just like Verilog.”
“Real hardware doesn't have any delta cycles or determinism issues due to scheduling.”
“Verilog and SystemVerilog allow me to do this efficiently. Warts and all.”
“yet the Verilog model has given me less issues in practice”
“The beauty and the terror of Verilog is the complete, unconstrained parallel nature of it’s default”
“The world's most complex chips are built with it.”
“fail as soon as the scenario becomes slightly complex.”
“even before you even get into stuff like Verilog”
“I like the strict typing much better than verilog”
“Verilog's unholy combination of C-like syntax with begin/end blocks, etc.”
“Verilog & VHDL's incredibly brittle baseline”
“Most of industry is still choosing VHDL or Verilog for most greenfield hardware projects.”
“Learn to fashion hardware in a language.”
“I'm even more amazed that Verilog can't gracefully handle multi-phase clocks”
“Digital IC design engineers have no problem with them.”
“Verilog is about as good at match as you are likely to get, if you stick with the source code approach”
“VHDL and Verilog are showing their age with their design as well as ther tooling ecosystem”
“both Verilog and VHDL are languages that were designed for simulation of hardware, and not synthesis of hardware”
“VHDL and Verilog are used because they are excellent languages to describe hardware”
“in VHDL and Verilog, people have successfully described parallel computations containing billions of concurrent processes”
Counts come from 1,795,640 Hacker News comments, November 2025 to November 2026. How we count. Report a mistake.