# Verilog

13 Hacker News commenters recommended Verilog and 16 criticized it, November 2025 to November 2026. It was recommended in 6 of 13 months.

**Verdict:** Widely used to describe digital chips; recommended for parallel modelling and mature tooling. Critics say it is clumsy and was designed for simulation, not synthesis.

## Why people recommend it

- Industry standard for chip design (2 comments): "Most of industry is still choosing VHDL or Verilog for most greenfield hardware projects." ([source](https://news.ycombinator.com/item?id=46818190)) "The world's most complex chips are built with it." ([source](https://news.ycombinator.com/item?id=47570967))
- Simulation and synthesis match well (3 comments): "Verilog is about as good at match as you are likely to get, if you stick with the source code approach" ([source](https://news.ycombinator.com/item?id=46363175)) "yet the Verilog model has given me less issues in practice" ([source](https://news.ycombinator.com/item?id=47571048)) "I've never had to chase sim vs synthesis mismatches." ([source](https://news.ycombinator.com/item?id=47577016))
- Describes parallel hardware naturally (2 comments): "in VHDL and Verilog, people have successfully described parallel computations containing billions of concurrent processes" ([source](https://news.ycombinator.com/item?id=45834242)) "The beauty and the terror of Verilog is the complete, unconstrained parallel nature of it’s default" ([source](https://news.ycombinator.com/item?id=47571002))
- Efficient for hardware work (2 comments): "VHDL and Verilog are used because they are excellent languages to describe hardware" ([source](https://news.ycombinator.com/item?id=46360989)) "Verilog and SystemVerilog allow me to do this efficiently. Warts and all." ([source](https://news.ycombinator.com/item?id=47571129))

## What people warn about

- Designed for simulation, not synthesis (2 comments): "both Verilog and VHDL are languages that were designed for simulation of hardware, and not synthesis of hardware" ([source](https://news.ycombinator.com/item?id=46361322)) "It's also very lossy (every vendor has reams of coding guides for using it just right with their synthetizer)." ([source](https://news.ycombinator.com/item?id=49601989))
- Clumsy, error-prone, painful to write (4 comments): "Verilog felt like a joke of a language designed to torment rather than help the user" ([source](https://news.ycombinator.com/item?id=47840866)) "writing VHDL or Verilog is universally a fairly miserable experience" ([source](https://news.ycombinator.com/item?id=50227978)) "All to avoid the painful memories I have of verilog/vhdl." ([source](https://news.ycombinator.com/item?id=49238620))
- Missing fixed-point and multi-phase clocks (2 comments): "Verilog's type system is insufficiently expressive to add fixed-point types without changes to the language itself." ([source](https://news.ycombinator.com/item?id=47578330)) "I'm even more amazed that Verilog can't gracefully handle multi-phase clocks" ([source](https://news.ycombinator.com/item?id=46700835))
- Dated tooling and wrong abstraction (2 comments): "VHDL and Verilog are showing their age with their design as well as ther tooling ecosystem" ([source](https://news.ycombinator.com/item?id=46361762)) "VHDL and verilog are simply at the wrong abstraction level" ([source](https://news.ycombinator.com/item?id=47578279))

## Alternatives hackers recommend

- [Chisel](https://hackerapproved.com/p/chisel.md): 7 recommend
- [SHDL](https://hackerapproved.com/p/shdl.md): 6 recommend
- [Clash (Haskell-to-HDL compiler)](https://hackerapproved.com/p/clash.md): 5 recommend

## Cite as

Hacker Approved, "Verilog", https://hackerapproved.com/p/verilog/ (counts from 1,795,640 Hacker News comments, November 2025 to November 2026).